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RAHMAN ARIFUR

Overview
  • Total Patents
    21
About

RAHMAN ARIFUR has a total of 21 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, computer technology and measurement are CHIN MEITO, BOTULA ALAN B and WU ALBERT.

Patent filings in countries

World map showing RAHMAN ARIFURs patent filings in countries
# Country Total Patents
#1 United States 21

Patent filings per year

Chart showing RAHMAN ARIFURs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Rahman Arifur 21
#2 Pan Hong-Tsz 2
#3 Xie Yuanlin 1
#4 Wu Zhaoyin D 1
#5 Chaware Raghunandan 1
#6 Kim Namhoon 1
#7 Hart Michael J 1
#8 Nguyen Bang-Thu 1
#9 Liu Henley 1
#10 Chen Min-Hsing 1

Latest patents

Publication Filing date Title
US8802454B1 Methods of manufacturing a semiconductor structure
US9330823B1 Integrated circuit structure with inductor in silicon interposer
US2013069247A1 Apparatus for stacked electronic circuitry and associated methods
US2012331435A1 Integrated circuit design using through silicon vias
US2012319248A1 Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone
US2012139102A1 Disposing underfill in an integrated circuit structure
US8216936B1 Low capacitance electrical connection via
US8886481B1 Reducing variation in multi-die integrated circuits
US8156456B1 Unified design methodology for multi-die integrated circuits
US2011316572A1 Testing die-to-die bonding and rework
US8332803B1 Method and apparatus for integrated circuit package thermo-mechanical reliability analysis
US8237274B1 Integrated circuit package with redundant micro-bumps
US8933345B1 Method and apparatus for monitoring through-silicon vias
US8933447B1 Method and apparatus for programmable device testing in stacked die applications
US2011012633A1 Apparatus and method for testing of stacked die structure
US8089299B1 Integrated circuit with through-die via interface for die stacking and cross-track routing
US8296689B1 Customizing metal pattern density in die-stacking applications
US8987868B1 Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US8082537B1 Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
US2009224400A1 Semiconductor assembly having reduced thermal spreading resistance and methods of making same