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CHEN HSIEN-WEI

Overview
  • Total Patents
    39
About

CHEN HSIEN-WEI has a total of 39 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, audio-visual technology and optics are ADVANCED INTERCONNECT TECH LTD, CHI HEEJO and J DEVICES:KK.

Patent filings in countries

World map showing CHEN HSIEN-WEIs patent filings in countries
# Country Total Patents
#1 United States 39

Patent filings per year

Chart showing CHEN HSIEN-WEIs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Chen Hsien-Wei 39
#2 Tsai Hao-Yi 9
#3 Jeng Shin-Puu 8
#4 Chen Ying-Ju 7
#5 Liu Yu-Wen 5
#6 Yang Chung-Ying 5
#7 Yu Chen-Hua 3
#8 Hsu Shih-Hsun 3
#9 Wu Yi-Wen 2
#10 Lii Mirng-Ji 2

Latest patents

Publication Filing date Title
US2014077356A1 Post passivation interconnect structures and methods for forming the same
US2014061923A1 Structure to increase resistance to electromigration
US2014045379A1 Package assembly and methods for forming the same
US2013270698A1 Strain reduced structure for IC packaging
US2013270710A1 Guard ring design structure for semiconductor devices
US2013270686A1 Methods and apparatus for heat spreader on silicon
US2013228897A1 Electrical connections for chip scale packaging
US2013207258A1 Post-passivation interconnect structure AMD method of forming same
US2013187266A1 Integrated circuit package assembly and method of forming the same
US2013147034A1 Bump structure design for stress reduction
US2013147033A1 Post-passivation interconnect structure
US2013147031A1 Semiconductor device with bump structure on an interconncet structure
US2013093084A1 Wafer-level chip scale package with re-workable underfill
US2011284843A1 Probe pad on a corner stress relief region in a semiconductor chip
US2013026618A1 Method and device for circuit routing by way of under-bump metallization
US2013015561A1 Mechanisms for marking the orientation of a sawed die
US2012299167A1 Uniformity control for IC passivation structure
US2012299159A1 Structure designs and methods for integrated circuit alignment
US2012091578A1 Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same
US2012180018A1 Increasing dielectric strength by optimizing dummy metal distribution