Learn more

LIN JING-CHENG

Overview
  • Total Patents
    35
About

LIN JING-CHENG has a total of 35 patent applications. Its first patent ever was published in 2004. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, machines and electrical machinery and energy are UNITED TEST & ASSEMBLY CT LTD, UNISEM MAURITIUS HOLDINGS LTD and KWON HEUNG-KYU.

Patent filings in countries

World map showing LIN JING-CHENGs patent filings in countries
# Country Total Patents
#1 United States 35

Patent filings per year

Chart showing LIN JING-CHENGs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lin Jing-Cheng 35
#2 Yu Chen-Hua 14
#3 Lu Szu Wei 9
#4 Jeng Shin-Puu 8
#5 Hung Jui-Pin 8
#6 Tsai Po-Hao 5
#7 Huang Cheng-Lin 4
#8 Kuo Li-Chung 2
#9 Chiou Wen-Chih 2
#10 Shih Ying-Ching 2

Latest patents

Publication Filing date Title
US2014061897A1 Bump structures for semiconductor package
US2014001645A1 3DIC stacking device and method of manufacture
US2014061888A1 Three dimensional (3D) fan-out packaging mechanisms
US2013307143A1 Wafer-level packaging mechanisms
US2013249532A1 Probing chips during package formation
US2013223014A1 Mechanisms for controlling bump height variation
US2013134559A1 Chip-on-Wafer structures and methods for forming the same
US2013210198A1 Process for forming semiconductor structure
US2013200529A1 Semiconductor device packaging methods and structures thereof
US2013193593A1 Bump structural designs to minimize package defects
US2013168848A1 Packaged semiconductor device with a molding compound and a method of forming the same
US2013154062A1 Die structure and method of fabrication thereof
US2013134581A1 Planarized bumps for underfill control
US2013119552A1 Packages including active dies and dummy dies and methods for forming the same
US2013087951A1 Molding Chamber Apparatus and Curing Method
US2013087916A1 Methods of packaging semiconductor devices and structures thereof
US2013077272A1 Structure design for 3DIC testing
US2013075892A1 Method for Three Dimensional Integrated Circuit Fabrication
US2013056865A1 Method of three dimensional integrated circuit assembly
US2013049216A1 Die-to-die gap control for semiconductor structure and method