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GLOBALFOUNDRIES DRESDEN MOD 1

Overview
  • Total Patents
    254
  • GoodIP Patent Rank
    228,206
About

GLOBALFOUNDRIES DRESDEN MOD 1 has a total of 254 patent applications. Its first patent ever was published in 2007. It filed its patents most often in Germany, China and Republic of Korea. Its main competitors in its focus markets semiconductors, optics and computer technology are CHEN HSIEN-WEI, YU CHEN-HUA and YANG WEN-KUN.

Patent filings in countries

World map showing GLOBALFOUNDRIES DRESDEN MOD 1s patent filings in countries
# Country Total Patents
#1 Germany 244
#2 China 4
#3 Republic of Korea 4
#4 Taiwan 1
#5 United States 1

Patent filings per year

Chart showing GLOBALFOUNDRIES DRESDEN MOD 1s patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Hoentschel Jan 42
#2 Scheiper Thilo 41
#3 Kronholz Stephan 40
#4 Beyer Sven 39
#5 Frohberg Kai 31
#6 Griebenow Uwe 25
#7 Lenski Markus 24
#8 Wei Andy 23
#9 Heinrich Jens 22
#10 Richter Ralf 22

Latest patents

Publication Filing date Title
US10909298B1 Well contact cell with doped tap region separated from active region, and methods to form same
DE102011005718A1 A method of reducing the equivalent thickness of high-k dielectrics in field effect transistors by performing a low temperature anneal process
DE102011005719A1 Increased integrity of large ε metal gate stacks by reducing STI settlements by depositing a filler after STI fabrication
DE102011005639A1 Reduce the defect rate during the deposition of a channel semiconductor alloy into an in situ lowered active area
DE102011005641A1 A method of increasing performance in transistors by reducing subsidence of active regions and by removing spacers
DE102011005642A1 A method for protecting reactive metal surfaces of semiconductor devices during transport by providing an additional protective layer
DE102011004921A1 Semiconductor device with a chip border with an integrated alignment mark
DE102011004922A1 Method of fabricating transistors with metal gate stacks with increased integrity
DE102011004757A1 Vertical memory transistors having a self-adjusting body potential fabricated in bulk substrate devices and having buried interrogation and word lines and methods of fabricating the memory transistors
DE102011004672A1 SOI semiconductor device having a substrate diode with reduced metal silicide leakage
DE102011004581A1 A technique for reducing plasma-induced etch damage during the fabrication of vias in inter-layer dielectrics by modified RF power ramp-up
DE102011004506A1 A method of fabricating a semiconductor device and semiconductor device as a fin transistor fabricated on a patterned STI region by a late stage etch
DE102011004320A1 Method for producing complementary transistors with metal gate electrode structures with large ε and epitaxially produced semiconductor materials in the drain and source regions
DE102011004322A1 A method of manufacturing a semiconductor device having self-aligned contact elements and an exchange gate electrode structure
DE102011004323A1 Semiconductor device with self-aligned contact elements and method for its production
DE102011003439A1 Method for forward current increase in field effect transistors by asymmetric concentration profiles of alloying materials of a channel semiconductor alloy and semiconductor device
DE102011003385A1 Method for producing a semiconductor structure with deformation-inducing semiconductor material
DE102011003232A1 A manufacturing method for large-sized metal gate electrode structures made by an exchange gate method based on improved flatness of dummy materials
DE102011002877A1 A method of making an SOI semiconductor device having a substrate diode and a layered diode fabricated using a common well implantation mask
DE102011002769A1 A semiconductor device and method of making a hybrid contact structure having small aspect ratio contacts in a semiconductor device