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CHOI DAESIK

Overview
  • Total Patents
    28
About

CHOI DAESIK has a total of 28 patent applications. Its first patent ever was published in 2008. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and audio-visual technology are 3DIS TECH, PAGAILA REZA A and CHI HEEJO.

Patent filings in countries

World map showing CHOI DAESIKs patent filings in countries
# Country Total Patents
#1 United States 28

Patent filings per year

Chart showing CHOI DAESIKs patent filings per year from 1900 to 2020

Focus industries

Focus technologies

Top inventors

# Name Total Patents
#1 Choi Daesik 28
#2 Cho Sungwon 4
#3 Park Sang Mi 4
#4 Lee Taewoo 4
#5 Lee Kyuwon 3
#6 Yang Joungin 3
#7 Kim Minjung 3
#8 Yu Minwook 3
#9 Choi Joonyoung 2
#10 Yun Jaeun 2

Latest patents

Publication Filing date Title
US2013300004A1 Semiconductor device and method of controlling warpage in semiconductor package
US2013221543A1 Integrated circuit packaging system with interconnects
US2013154116A1 Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereof
US2013154085A1 Integrated circuit packaging system with heat conduction and method of manufacture thereof
US2013154078A1 Integrated circuit packaging system with heat slug and method of manufacture thereof
US2013105963A1 Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die
US2013075916A1 Integrated circuit packaging system with external wire connection and method of manufacture thereof
US2013049188A1 Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
US2013037936A1 Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
US2012326291A1 Integrated circuit packaging system with underfill and method of manufacture thereof
US2012306104A1 Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US2012286407A1 Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die
US2012280374A1 Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US2012273937A1 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
US2012273938A1 Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar
US2012241979A1 Integrated circuit packaging system with step mold and method of manufacture thereof
US2012211900A1 Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer
US2012146235A1 Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US2012104624A1 Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US2012068319A1 Integrated circuit packaging system with stack interconnect and method of manufacture thereof