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PAGAILA REZA A

Overview
  • Total Patents
    77
About

PAGAILA REZA A has a total of 77 patent applications. Its first patent ever was published in 2008. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and audio-visual technology are 3DIS TECH, CHOI DAESIK and DO BYUNG TAI.

Patent filings in countries

World map showing PAGAILA REZA As patent filings in countries
# Country Total Patents
#1 United States 77

Patent filings per year

Chart showing PAGAILA REZA As patent filings per year from 1900 to 2020

Focus industries

Focus technologies

Top inventors

# Name Total Patents
#1 Pagaila Reza A 77
#2 Do Byung Tai 34
#3 Lin Yaojian 22
#4 Koo Jun Mo 14
#5 Chua Linda Pei Ee 13
#6 Huang Shuangwu 9
#7 Merilo Dioscoro A 6
#8 Kuan Heap Hoe 4
#9 Huang Rui 4
#10 Camacho Zigmund R 4

Latest patents

Publication Filing date Title
US2013056867A1 Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die
US2012049388A1 Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation
US2012273926A1 Semiconductor device and method of forming shielding layer over active surface of semiconductor die
US2012228749A1 Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
US2012217645A1 Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US2012217644A1 Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
US2012217643A1 Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die
US2012104623A1 Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US2012061824A1 Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US2012061822A1 Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
US8080445B1 Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US2012056312A1 Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US2012056314A1 Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US8097490B1 Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US2012049334A1 Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US2012049344A1 Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US2012012990A1 Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US2011316146A1 Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
US2011316156A1 Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US2011316132A1 Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe