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STATS CHIPPAC LTD

Overview
  • Total Patents
    1,662
  • GoodIP Patent Rank
    8,599
About

STATS CHIPPAC LTD has a total of 1,662 patent applications. Its first patent ever was published in 1999. It filed its patents most often in United States, Singapore and Taiwan. Its main competitors in its focus markets semiconductors, audio-visual technology and machines are J-DEVICES CORP, CHIPPAC INC and SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD.

Patent filings in countries

World map showing STATS CHIPPAC LTDs patent filings in countries

Patent filings per year

Chart showing STATS CHIPPAC LTDs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lin Yaojian 324
#2 Chow Seng Guan 207
#3 Do Byung Tai 181
#4 Shim Il Kwon 179
#5 Kuan Heap Hoe 148
#6 Pagaila Reza A 138
#7 Chen Kang 138
#8 Pendse Rajendra D 109
#9 Camacho Zigmund Ramirez 99
#10 Tay Lionel Chien Hui 92

Latest patents

Publication Filing date Title
US2016300797A1 Double-sided semiconductor package and dual-mold method of making same
US2016300817A1 Semiconductor device and method of forming a package in-fan out package
US2016214857A1 Semiconductor device and method of forming MEMS package
US2016118333A1 Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US2016118332A1 Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US2016013148A1 Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
US2016043047A1 Semiconductor device and method of forming double-sided fan-out wafer level package
US2015325553A1 Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP
US2016351486A1 Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US2015348936A1 Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits
KR20150126562A Integrated circuit packaging system with no-reflow connection and method of manufacture thereof
US2016276307A1 Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US2015259194A1 Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US2015243575A1 Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
US2015179616A1 Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US2015155248A1 Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US2015097295A1 Semiconductor device and method of forming conductive layer over substrate with vents to channel bump material and reduce interconnect voids
US2015091165A1 Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration
SG10201408088SA Integrated circuit packaging system with embedded component and method of manufacture thereof
US2015140736A1 Semiconductor device and method of forming wire bondable fan-out EWLB package