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LIN YAOJIAN

Overview
  • Total Patents
    74
About

LIN YAOJIAN has a total of 74 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, audio-visual technology and machines are PAGAILA REZA ARGENTY, ASAT LTD and MEYER-BERG GEORG.

Patent filings in countries

World map showing LIN YAOJIANs patent filings in countries
# Country Total Patents
#1 United States 74

Patent filings per year

Chart showing LIN YAOJIANs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lin Yaojian 74
#2 Chen Kang 40
#3 Fang Jianmin 28
#4 Cao Haijing 24
#5 Marimuthu Pandi Chelvam 10
#6 Zhang Qing 10
#7 Feng Xia 8
#8 Frye Robert C 7
#9 Gu Yu 5
#10 Caparas Jose Alvin 3

Latest patents

Publication Filing date Title
US2013320525A1 Integrated circuit packaging system with substrate and method of manufacture thereof
US2013341784A1 Semiconductor device and method of forming an embedded SOP fan-out package
US2013069227A1 Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US2013249101A1 Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US2012205813A1 Integrated circuit package system with post-passivation interconnection and integration
US2013249115A1 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US2013249106A1 Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US2013249080A1 Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation
US2013249105A1 Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief
US2012112340A1 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US2012187568A1 Semiconductor device and method of forming FO-WLCSP with multiple encapsulants
US2013154108A1 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US2013147054A1 Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
US2012161279A1 Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US2013075924A1 Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
US2013075936A1 Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US2013069225A1 Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US2013069241A1 Semiconductor device and method of forming semiconductor package using panel form carrier
US2011278736A1 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US2012018904A1 Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis