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STATS CHIPPAC PTE LTD

Overview
  • Total Patents
    189
  • GoodIP Patent Rank
    8,363
  • Filing trend
    ⇩ 17.0%
About

STATS CHIPPAC PTE LTD has a total of 189 patent applications. It decreased the IP activity by 17.0%. Its first patent ever was published in 2010. It filed its patents most often in United States, Republic of Korea and Singapore. Its main competitors in its focus markets semiconductors, audio-visual technology and micro-structure and nano-technology are TERAMIKROS INC, CHI HEEJO and J DEVICES:KK.

Patent filings in countries

World map showing STATS CHIPPAC PTE LTDs patent filings in countries
# Country Total Patents
#1 United States 117
#2 Republic of Korea 25
#3 Singapore 20
#4 Taiwan 15
#5 China 12

Patent filings per year

Chart showing STATS CHIPPAC PTE LTDs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lin Yaojian 74
#2 Shim Il Kwon 40
#3 Chen Kang 30
#4 Marimuthu Pandi C 27
#5 Yang Deokkyung 25
#6 Cho Sungwon 24
#7 Kim Changoh 20
#8 Lee Hunteak 20
#9 Lee Heesoo 19
#10 Koo Kyowang 18

Latest patents

Publication Filing date Title
US2021028122A1 EMI Shielding for Flip Chip Package with Exposed Die Backside
US2020051926A1 EMI shielding for flip chip package with exposed die backside
US2020211977A1 Shielded semiconductor packages with open terminals and methods of making via two-step process
US2020211976A1 Semiconductor device with partial EMI shielding removal using laser ablation
US2020194379A1 Shielded semiconductor package with open terminal and methods of making
US2020161252A1 Molded laser package with electromagnetic interference shield and method of making
TW201926625A Antenna in embedded wafer-level ball-grid array package
US2019088603A1 Antenna in embedded wafer-level ball-grid array package
US2020144198A1 Method and Device for Reducing Metal Burrs When Sawing Semiconductor Packages
US2020075502A1 Semiconductor Device with Partial EMI Shielding and Method of Making the Same
US2020013738A1 Semiconductor device and method of forming protrusion E-bar for 3D SIP
US2018261569A1 Semiconductor device and method of forming a 3D interposer system-in-package module
US2019318984A1 Semiconductor Device and Method of Forming Conductive Vias to Have Enhanced Contact to Shielding Layer
US2019287873A1 Method of packaging thin die and semiconductor device including thin die
TW201836091A Semiconductor device and method of controlling warpage in reconstituted wafer
US2018158768A1 Semiconductor device and method of forming a 3D interposer system-in-package module
US2018158779A1 Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
US2019088621A1 Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
US2019074267A1 Semiconductor device and method of forming a 3D integrated system-in-package module
US2018061806A1 Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant