OPTIMALTEST LTD has a total of 20 patent applications. Its first patent ever was published in 2005. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and EPO (European Patent Office). Its main competitors in its focus markets measurement, computer technology and semiconductors are ON CHIP TECHNOLOGIES INC, SYNC-TECH SYSTEM CORP and TEKUMALLA RAMESH C.
# | Country | Total Patents | |
---|---|---|---|
#1 | United States | 9 | |
#2 | WIPO (World Intellectual Property Organization) | 5 | |
#3 | EPO (European Patent Office) | 3 | |
#4 | Taiwan | 3 |
# | Industry | |
---|---|---|
#1 | Measurement | |
#2 | Computer technology | |
#3 | Semiconductors |
# | Technology | |
---|---|---|
#1 | Measuring electric variables | |
#2 | Specific computer systems | |
#3 | Static stores | |
#4 | Semiconductor devices |
# | Name | Total Patents |
---|---|---|
#1 | Balog Gil | 18 |
#2 | Linde Reed | 6 |
#3 | Golan Avi | 5 |
#4 | Gurov Leonid | 2 |
#5 | Chufarovsky Alexander | 2 |
#6 | Erez Nir | 2 |
#7 | Glotter Dan | 1 |
Publication | Filing date | Title |
---|---|---|
WO2012063244A1 | Misalignment indication decision system and method | |
WO2010073245A1 | System and methods for parametric testing | |
US2009192754A1 | Systems and methods for test time outlier detection and correction in integrated circuit testing | |
WO2008081419A2 | Systems and methods for test time outlier detection and correction in integrated circuit testing | |
US2008007284A1 | Methods and systems for semiconductor testing using reference dice | |
US2007233629A1 | Methods and systems for semiconductor testing using a testing scenario language | |
US2006267577A1 | Augmenting semiconductor's devices quality and reliability | |
US2007007981A1 | Optimize parallel testing |