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US2014032985A1
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Scan test circuitry configured to prevent capture of potentially non-deterministic values
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Scan controller configured to control signal values applied to signal lines of circuit core input interface
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US2013290799A1
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Scan test circuitry with selectable transition launch mode
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US2013275824A1
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Scan-based capture and shift of interface functional signal values in conjunction with built-in self-test
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Integrated circuit having clock gating circuitry responsive to scan shift control signal
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US2013185607A1
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Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
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US2013179742A1
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Scan chain lockup latch with data input control responsive to scan enable signal
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US2013173976A1
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Scan test circuitry with delay defect bypass functionality
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US2013111286A1
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Scan enable timing control for testing of scan cells
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US2013103994A1
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Dynamic clock domain bypass for scan chains
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US2013067290A1
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Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing
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US2013055041A1
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Scan test circuitry comprising scan cells with multiple scan inputs
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US2012246529A1
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Low-power and area-efficient scan cell for integrated circuit testing
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US2013007547A1
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Efficient wrapper cell design for scan testing of integrated
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US2012331362A1
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Integrated circuit comprising scan test circuitry with controllable number of capture pulses
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US2012324303A1
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Integrated circuit comprising scan test circuitry with parallel reordered scan chains
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