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XUE YAN XUN

Overview
  • Total Patents
    27
  • GoodIP Patent Rank
    215,515
About

XUE YAN XUN has a total of 27 patent applications. Its first patent ever was published in 2009. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and machines are HVVI SEMICONDUCTORS INC, DAWNING LEADING TECH INC and CHO NAMJU.

Patent filings in countries

World map showing XUE YAN XUNs patent filings in countries
# Country Total Patents
#1 United States 27

Patent filings per year

Chart showing XUE YAN XUNs patent filings per year from 1900 to 2020

Focus industries

Top inventors

# Name Total Patents
#1 Xue Yan Xun 27
#2 Lu Jun 20
#3 Ho Yueh-Se 14
#4 Yilmaz Hamza 12
#5 Shi Lei 7
#6 Bhalla Anup 7
#7 Zhao Liang 6
#8 Huang Ping 6
#9 Gong Yuping 2
#10 Duan Lei 2

Latest patents

Publication Filing date Title
US2015262925A1 Semiconductor device employing aluminum alloy lead-frame with anodized aluminum
US2015249045A1 Power semiconductor device and preparation method thereof
US2015162257A1 Method and structure for wafer level packaging with large contact area
US2015087114A1 Method for packaging a power device with bottom source electrode
US8778735B1 Packaging method of molded wafer level chip scale package (WLCSP)
US2014361419A1 Packaged power semiconductor with interconnection of dies and metal clips on lead frame
US2014361418A1 Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes
US2014191334A1 Stacked power semiconductor device using dual lead frame
US2014091446A1 Semiconductor device employing aluminum alloy lead-frame with anodized aluminum
US2013037917A1 Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
US2013210195A1 Packaging method of molded wafer level chip scale package (WLCSP)
US2012235289A1 Power device with bottom source electrode
US2013037962A1 Wafer level packaging structure with large contact area and preparation method thereof
US2013210215A1 Packaging method with backside wafer dicing
US2013037935A1 Wafer level package structure and the fabrication method thereof
US2012299119A1 Stacked power semiconductor device using dual lead frame and manufacturing method
US2011193208A1 Semiconductor package of a flipped MOSFET and its manufacturing method
US2012164794A1 Method of making a copper wire bond package
US2012146202A1 Top exposed package and assembly method
US2011062506A1 Metal oxide semiconductor field effect transistor integrating a capacitor