|
US8563403B1
|
|
Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
|
|
US2013334691A1
|
|
Sidewalls of electroplated copper interconnects
|
|
US2013307160A1
|
|
Via structure for three-dimensional circuit integration
|
|
US2013260556A1
|
|
Bottom-up plating of through-substrate vias
|
|
US2013119509A1
|
|
Forming BEOL line fuse structure
|
|
US2013026606A1
|
|
TSV pillar as an interconnecting structure
|
|
US2012315753A1
|
|
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
|
|
US2012280395A1
|
|
3-D integration using multi stage vias
|
|
US8237288B1
|
|
Enhanced electromigration resistance in tsv structure and design
|
|
US2012175789A1
|
|
Alignment marks to enable 3D integration
|
|
US2012018851A1
|
|
Metal-contamination-free through-substrate via structure
|
|
US2011237026A1
|
|
Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
|
|
US2011193240A1
|
|
Bonded structure with enhanced adhesion strength
|
|
US2011193197A1
|
|
Structure and method for making crack stop for 3D integrated circuits
|
|
US2010193964A1
|
|
Method of making 3D integrated circuits
|
|
US2011180920A1
|
|
Co-axial restraint for connectors within flip-chip packages
|
|
US2011175215A1
|
|
3D chip stack having encapsulated chip-in-chip
|
|
US2011171582A1
|
|
Three dimensional integration with through silicon vias having multiple diameters
|
|
US2011171827A1
|
|
Three dimensional integration and methods of through silicon via creation
|
|
US2011168434A1
|
|
Bonded structure employing metal semiconductor alloy bonding
|
