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US2013341724A1
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FinFET with body contact
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Plural differential pair employing FinFET structure
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Implementing isolated silicon regions in silicon-on-insulator (soi) wafers using bonded-wafer technique
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Utilizing gate phases for circuit tuning
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Deep trench embedded gate transistor
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Independently voltage controlled volume of silicon on a silicon on insulator chip
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US2012268195A1
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Implementing eFuse circuit with enhanced eFuse blow operation
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Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit
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eDRAM having dynamic retention and performance tradeoff
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US2012175624A1
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Implementing vertical signal repeater transistors utilizing wire vias as gate nodes
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US2012175626A1
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Implementing semiconductor SoC with metal via gate node high performance stacked transistors
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Enhanced thin film field effect transistor integration into back end of line
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Vertically stacked FETs with series bipolar junction transistor
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US2011298052A1
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Vertical Stacking of Field Effect Transistor Structures for Logic Gates
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