|
US2014070393A1
|
|
Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks
|
|
US2013277798A1
|
|
Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies
|
|
US2013254473A1
|
|
Implementing memory interface with configurable bandwidth
|
|
US2013001676A1
|
|
Through silicon via direct FET signal gating
|
|
US2012211829A1
|
|
Field-effect transistor and method of creating same
|
|
US2012146711A1
|
|
Power domain controller with gated through silicon via having FET with horizontal channel
|
|
US2012098140A1
|
|
Hybrid bonding techniques for multi-layer semiconductor stacks
|
|
US2012038057A1
|
|
Thermal enhancement for multi-layer semiconductor stacks
|
|
US2012007229A1
|
|
Enhanced thermal management of 3-D stacked die packaging
|
|
US2011238879A1
|
|
Sorting movable memory hierarchies in a computer system
|
|
US2010271071A1
|
|
Universal inter-layer interconnect for multi-layer semiconductor stacks
|
|
US2010185410A1
|
|
Three dimensional chip fabrication
|
|
US2010025479A1
|
|
Doped implant monitoring for microchip tamper detection
|
|
US2010026326A1
|
|
Resistance sensing for defeating microchip exploitation
|
|
US2010031376A1
|
|
Continuity check monitoring for microchip exploitation detection
|
|
US2010031375A1
|
|
Signal quality monitoring to defeat microchip exploitation
|
|
US2008177951A1
|
|
Structure for multi-level memory architecture with data prioritization
|
|
US2007236895A1
|
|
Via resistor structure and method for trimming resistance value
|
