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WORLDWIDE SEMICONDUCTOR MFG

Overview
  • Total Patents
    77
About

WORLDWIDE SEMICONDUCTOR MFG has a total of 77 patent applications. Its first patent ever was published in 1997. It filed its patents most often in United States and Taiwan. Its main competitors in its focus markets semiconductors, machines and optics are PROMOS TECHNOLOGIES INC, WORLDWIDE SEMICONDUCTOR MANUFA and DONGBUANAM SEMICONDUCTOR INC.

Patent filings in countries

World map showing WORLDWIDE SEMICONDUCTOR MFGs patent filings in countries
# Country Total Patents
#1 United States 67
#2 Taiwan 10

Patent filings per year

Chart showing WORLDWIDE SEMICONDUCTOR MFGs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Lou Chine-Gie 20
#2 Linliu Kung 6
#3 Wang Ling-Sung 6
#4 Chi Min-Hwa 5
#5 Tu Yeur-Luen 4
#6 Niu Pao-Kang 3
#7 Luo Ji-Jin 3
#8 Du You-Luen 3
#9 Liu Chia-Chen 3
#10 Lien Wan-Yih 3

Latest patents

Publication Filing date Title
US6281059B1 Method of doing ESD protective device ion implant without additional photo mask
US6343977B1 Multi-zone conditioner for chemical mechanical polishing system
US6150235A Method of forming shallow trench isolation structures
US6410441B1 Auto slurry deliver fine-tune system for chemical-mechanical-polishing process and method of using the system
US6479401B1 Method of forming a dual-layer anti-reflective coating
US6160286A Method for operation of a flash memory using n+/p-well diode
US6281089B1 Method for fabricating an embedded flash memory cell
US6087695A Source side injection flash EEPROM memory cell with dielectric pillar and operation
US6163482A One transistor EEPROM cell using ferro-electric spacer
US6084262A Etox cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current
US6338993B1 Method to fabricate embedded DRAM with salicide logic cell structure
US6255164B1 EPROM cell structure and a method for forming the EPROM cell structure
US6261906B1 Method for forming a flash memory cell with improved drain erase performance
US6200881B1 Method of forming a shallow trench isolation
US6147005A Method of forming dual damascene structures
US6222201B1 Method of forming a novel self-aligned offset thin film transistor and the structure of the same
US6236080B1 Method of manufacturing a capacitor for high density DRAMs
US6228753B1 Method of fabricating a bonding pad structure for improving the bonding pad surface quality
US6162680A Method for forming a DRAM capacitor
US6133151A HDP-CVD method for spacer formation