Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant
US6130462A
Vertical poly load device in 4T SRAM technology
US6060742A
ETOX cell having bipolar electron injection for substrate-hot-electron program
US6110790A
Method for making a MOSFET with self-aligned source and drain contacts including forming an oxide liner on the gate, forming nitride spacers on the liner, etching the liner, and forming contacts in the gaps
US6107660A
Vertical thin film transistor
US6040603A
Electrostatic discharge protection circuit employing MOSFETs having double ESD implantations
US6121082A
Method of fabricating DRAM with novel landing pad process
US6110837A
Method for forming a hard mask of half critical dimension
US6022776A
Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads
US6091635A
Electron injection method for substrate-hot-electron program and erase VT tightening for ETOX cell
US6025625A
Single-poly EEPROM cell structure operations and array architecture
US6088259A
SRAM cell using two single transistor inverters
US6096653A
Method for fabricating conducting lines with a high topography height
US6090679A
Method for forming a crown capacitor
US6101656A
Wafer cleaning device
US6100129A
Method for making fin-trench structured DRAM capacitor
US6111286A
Low voltage low power n-channel flash memory cell using gate induced drain leakage current
US5916823A
Method for making dual damascene contact
US6087690A
Single polysilicon DRAM cell with current gain
US6062955A
Installation for improving chemical-mechanical polishing operation
