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SPIN MEMORY INC

Overview
  • Total Patents
    170
  • GoodIP Patent Rank
    8,532
  • Filing trend
    ⇩ 10.0%
About

SPIN MEMORY INC has a total of 170 patent applications. It decreased the IP activity by 10.0%. Its first patent ever was published in 2016. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and EPO (European Patent Office). Its main competitors in its focus markets computer technology, semiconductors and electrical machinery and energy are SHANGHAI CIYU INFORMATION TECH CO LTD, KATTI ROMNEY R and TACHYON SEMICONDUCTOR CORP.

Patent filings per year

Chart showing SPIN MEMORY INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Kim Kuk-Hwan 38
#2 Pinarbasi Mustafa 38
#3 Kardasz Bartlomiej Adam 35
#4 Levi Amitay 35
#5 Beery Dafna 32
#6 Walker Andrew J 28
#7 Tzoufras Michail 28
#8 Gajek Marcin 26
#9 Berger Neal 24
#10 Bozdag Kadriye Deniz 22

Latest patents

Publication Filing date Title
US2021089455A1 Circuit engine for managing memory meta-stability
WO2021072370A1 Error cache system with coarse and fine segments for power optimization
WO2020167496A1 Multi-chip module for mram devices
WO2020142440A1 Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
US2020127052A1 Memory cell using selective epitaxial vertical channel mos selector transistor
WO2020131893A2 Spin-orbit torque magnetic memory array and fabrication thereof
WO2020131868A1 System and method for training artificial neural networks
US10854255B1 Vertical selector stt-MRAM architecture
US10957370B1 Integration of epitaxially grown channel selector with two terminal resistive switching memory element
US2020042450A1 Error cache segmentation for power reduction
US2020050545A1 Mram noise mitigation for write operations with simultaneous background operations
US2020043540A1 Bi-polar write scheme
US2020042451A1 Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow
US2020117592A1 Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments
US2020117610A1 Error cache system with coarse and fine segments for power optimization
US2020057687A1 MRAM noise mitigation for background operations by delaying verify timing
US2021090679A1 Measurement of MTJ in a compact memory array
US10937479B1 Integration of epitaxially grown channel selector with mram device
WO2020046595A1 A method of optimizing write voltage based on error buffer occupancy
US10840298B1 Vertical selector STT-MRAM architecture