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SHROFF MEHUL D

Overview
  • Total Patents
    28
  • GoodIP Patent Rank
    209,427
About

SHROFF MEHUL D has a total of 28 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, computer technology and micro-structure and nano-technology are SHANGHAI HUALI MICROELECTRONIC, KITAMURA MASAHIRO and ZGLUE INC.

Patent filings in countries

World map showing SHROFF MEHUL Ds patent filings in countries
# Country Total Patents
#1 United States 28

Patent filings per year

Chart showing SHROFF MEHUL Ds patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Shroff Mehul D 28
#2 Hall Mark D 15
#3 Travis Edward O 8
#4 Reber Douglas M 7
#5 Stout Phillip J 1
#6 Johnstone William F 1
#7 Weintraub Chad E 1
#8 Parihar Sanjay R 1
#9 Adetutu Olubunmi O 1
#10 Grudowski Paul 1

Latest patents

Publication Filing date Title
US2015348898A1 Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures
US9112056B1 Method for forming a split-gate device
US2015249140A1 Method of making a logic transistor and non-volatile memory (NVM) cell
US2015035151A1 Capping layer interface interruption for stress migration mitigation
US8832624B1 Multi-layer process-induced damage tracking and remediation
US2014353797A1 Fuse/resistor utilizing interconnect and vias and method of making
US2014123085A1 Systems and methods for determining aging damage for semiconductor devices
US8595667B1 Via placement and electronic circuit design processing method and electronic circuit design utilizing same
US2014120713A1 Method of making a logic transistor and a non-volatile memory (NVM) cell
US8601430B1 Device matching tool and methods thereof
US8574987B1 Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric
US2013305202A1 Mismatch verification device and methods thereof
US2013171786A1 Non-volatile memory (NVM) and logic integration
US2013171785A1 Non-volatile memory (NVM) and logic integration
US2013147051A1 Method of protecting against via failure and structure therefor
US2013137227A1 Logic and non-volatile memory (NVM) integration
US2013055184A1 Method and system for physical verification using network segment current
US2013043540A1 Implant for performance enhancement of selected transistors in an integrated circuit
US2012267758A1 Isolated capacitors within shallow trench isolation
US2012267759A1 Decoupling capacitors recessed in shallow trench isolation