US2006028881A1
|
|
Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
|
US2006007773A1
|
|
Negative differential resistance (NDR) elements and memory device using the same
|
US6956262B1
|
|
Charge trapping pull up element
|
US7005711B2
|
|
N-channel pull-up element and logic circuit
|
US6806117B2
|
|
Methods of testing/stressing a charge trapping device
|
US7012833B2
|
|
Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
|
US6812084B2
|
|
Adaptive negative differential resistance device
|
US6979580B2
|
|
Process for controlling performance characteristics of a negative differential resistance (NDR) device
|
US6980467B2
|
|
Method of forming a negative differential resistance device
|
US6849483B2
|
|
Charge trapping device and method of forming the same
|
US6724024B1
|
|
Field effect transistor pull-up/load element
|
US6864104B2
|
|
Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
|
US6795337B2
|
|
Negative differential resistance (NDR) elements and memory device using the same
|
US6847562B2
|
|
Enhanced read and write methods for negative differential resistance (NDR) based memory device
|
US6567292B1
|
|
Negative differential resistance (NDR) element and memory with reduced soft error rate
|
US6518589B2
|
|
Dual mode FET & logic circuit having negative differential resistance mode
|
US6724655B2
|
|
Memory cell using negative differential resistance field effect transistors
|
US6754104B2
|
|
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
|
US6479862B1
|
|
Charge trapping device and method for implementing a transistor having a negative differential resistance mode
|
US6512274B1
|
|
CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
|