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CAMACHO ZIGMUND R

Overview
  • Total Patents
    24
About

CAMACHO ZIGMUND R has a total of 24 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors and audio-visual technology are HUATAI ELECTRONIC CO LTD, ELEC TECH WUHU CO LTD and PING XU.

Patent filings in countries

World map showing CAMACHO ZIGMUND Rs patent filings in countries
# Country Total Patents
#1 United States 24

Patent filings per year

Chart showing CAMACHO ZIGMUND Rs patent filings per year from 1900 to 2020

Focus industries

Focus technologies

Top inventors

# Name Total Patents
#1 Camacho Zigmund R 24
#2 Merilo Dioscoro A 13
#3 Tay Lionel Chien Hui 13
#4 Bathan Henry D 12
#5 Espiritu Emmanuel A 6
#6 Dahilig Frederick R 6
#7 Trasporto Arnel Senosa 3
#8 Punzalan Jeffrey D 3
#9 Pisigan Jairus L 2
#10 Min Wong Sze 1

Latest patents

Publication Filing date Title
US2013069222A1 Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US2012326337A1 Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
US2012299191A1 Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
US2012061814A1 Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US8076184B1 Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US2011215449A1 Semiconductor device and method of forming wafer level multi-row etched lead package
US2011215458A1 Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US2011140263A1 Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
US2010314780A1 Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers
US2010072599A1 Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US2009224386A1 Optical semiconductor device having pre-molded leadframe with window and method therefor
US2009166825A1 System and apparatus for wafer level integration of components
US2009140441A1 Wafer level die integration and method
US2007170558A1 Stacked integrated circuit package system