|
US2012327701A1
|
|
Memory array architecture with two-terminal memory cells
|
|
US8796658B1
|
|
Filamentary based non-volatile resistive memory device and method
|
|
US2013027081A1
|
|
Field programmable gate array utilizing two-terminal non-volatile memory
|
|
US2013027079A1
|
|
Field programmable gate array utilizing two-terminal non-volatile memory
|
|
US2012236650A1
|
|
NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
|
|
US2011305065A1
|
|
Non-volatile variable capacitive device including resistive memory cell
|
|
US2011305066A1
|
|
Write and erase scheme for resistive memory device
|
|
US2011080792A1
|
|
Parallel bitline nonvolatile memory employing channel-based processing technology
|
|
US2010122146A1
|
|
Error correction for flash memory
|
|
US2009113115A1
|
|
Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory
|
|
US2006238955A1
|
|
Re-configurable mixed-mode integrated circuit architecture
|
