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Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
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Vertical cross-point memory arrays
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Vertical cross point arrays for ultra high density memory applications
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Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
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Vertical gate NAND memory devices
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Low read current architecture for memory
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Planar resistive memory integration
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Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements
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Conductive metal oxide structures in non volatile re-writable memory devices
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Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
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Access signal adjustment circuits and methods for memory cells in a cross-point array
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Immersion platinum plating solution
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Structures And Methods For Facilitating Enhanced Cycling Endurance Of Memory Accesses To Re-Writable Non Volatile Two Terminal Memory Elements
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Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays
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Method of making a planar electrode
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Memory cell formation using ion implant isolated conductive metal oxide
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Data storage system with non-volatile memory using both page write and block program and block erase
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Conductive metal oxide structures in non-volatile re-writable memory devices
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Multi-structured memory
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High voltage switching circuitry for a cross-point array
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