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US2006133176A1
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Charge pump with ensured pumping capability
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Method and system for automatically validating a header search in reading data from an optical medium
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Integrated controller to process both optical reads and optical writes of multiple optical media
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Automated servo control system
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Method and system for window realignment using pipeline and sync correction to correct data frame boundaries
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Method and system for providing timing adjustment to perform reliable optical recording at high speeds
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Method and system for multiple column syndrome generation
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Semiconductor memory having predecoder control of spare column select lines
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Semiconductor memory having single path data pipeline for CAS-latency
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Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up
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Biasing an integrated circuit well with a transistor electrode
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Generation of signals from other signals that take time to develop on power-up
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Programmable circuits
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DRAM with new I/O data path configuration
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Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs
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DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle
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Charging a sense amplifier
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Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking
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I/O bias circuit insensitive to inadvertent power supply variations for MOS memory
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Charge storage for sensing operations in a DRAM
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