US2014075265A1
|
|
Outputting information of ECC corrected bits
|
US2014021935A1
|
|
Voltage buffer apparatus
|
US2013242665A1
|
|
Method and apparatus for shortened erase operation
|
US2012182804A1
|
|
Architecture for a 3D memory array
|
US2012182802A1
|
|
Memory architecture of 3D array with improved uniformity of bit line capacitances
|
US2012281471A1
|
|
Memory page buffer
|
US2012198298A1
|
|
On-the-fly repair method for memory
|
US2012007167A1
|
|
3D memory array with improved SSL and BL contact layout
|
US2012051137A1
|
|
Memory architecture of 3D array with diode in memory string
|
US2012063232A1
|
|
Method and apparatus for reducing read disturb in memory
|
US2012051130A1
|
|
System and method for detecting disturbed memory cells of a semiconductor memory device
|
US2012011300A1
|
|
Method and apparatus for high-speed byte-access in block-based flash memory
|
US2011060962A1
|
|
Method and apparatus for accessing memory with read error by changing comparison
|
US2011115551A1
|
|
Charge pump utilizing external clock signal
|
US2011085383A1
|
|
Current sink system for source-side sensing
|
US2011068837A1
|
|
Apparatus and method to tolerate floating input pin for input buffer
|
US2009296496A1
|
|
Method and circuit for testing a multi-chip package
|
US2009177817A1
|
|
Method and system for enhanced read performance in serial peripheral interface
|
US2008282107A1
|
|
Method and apparatus for repairing memory
|