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HALO LSI INC

Overview
  • Total Patents
    84
  • GoodIP Patent Rank
    214,907
About

HALO LSI INC has a total of 84 patent applications. Its first patent ever was published in 2000. It filed its patents most often in United States, Japan and Taiwan. Its main competitors in its focus markets computer technology, semiconductors and machines are LEE CHENG HUNG, YIELD MICROELECTRONICS CORP and INTEGRATED MEMORY TECH INC.

Patent filings per year

Chart showing HALO LSI INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Ogura Seiki 64
#2 Ogura Tomoko 56
#3 Saito Tomoya 34
#4 Ogura Nori 32
#5 Satoh Kimihiro 22
#6 Park Ki-Tae 8
#7 Baba Yoshitaka 5
#8 Hayashi Yutaka 3
#9 Sato Kimihiro 2
#10 Kirihara Masaharu 2

Latest patents

Publication Filing date Title
US2014219030A1 High density vertical structure nitride flash memory
US2010261324A1 Trap-charge non-volatile switch connector for programmable logic
WO2010024883A1 Complementary reference method for high reliability trap-type non-volatile memory
US2007030745A1 Referencing scheme for trap memory
US2006221706A1 Twin insulator charge storage device operation and its fabrication method
US2006187709A1 Twin insulator charge storage device operation and its fabrication method
US2007193683A1 Continuous pressed laminates
US2007047309A1 Twin MONOS array for high speed application
US2007047307A1 High speed operation method for twin MONOS metal bit array
US2005254305A1 Non-volatile memory dynamic operations
WO2005112035A2 Nonvolatile memory array organization and usage
US2004219751A1 Simplified twin monos fabrication method with three extra masks to standard CMOS
US7006378B1 Array architecture and operation methods for a nonvolatile memory
US7031192B1 Non-volatile semiconductor memory and driving method
US6876596B1 Decoder circuit with function of plural series bit line selection
US6999345B1 Method of sense and program verify without a reference cell for non-volatile semiconductor memory
US6900098B1 Twin insulator charge storage device operation and its fabrication method
US6914791B1 High efficiency triple well charge pump circuit
US6756271B1 Simplified twin monos fabrication method with three extra masks to standard CMOS
JP2003163292A Twin nand device structure, its array operation and its fabricating method