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GLOBAL FOUNDRIES INC

Overview
  • Total Patents
    56
  • GoodIP Patent Rank
    89,997
  • Filing trend
    ⇩ 100.0%
About

GLOBAL FOUNDRIES INC has a total of 56 patent applications. It decreased the IP activity by 100.0%. Its first patent ever was published in 2003. It filed its patents most often in United States, China and United Kingdom. Its main competitors in its focus markets semiconductors, computer technology and optics are REBER DOUGLAS M, SHANGHAI ZHUOHONG MICROSYSTEM TECH CO LTD and BECKER SCOTT T.

Patent filings in countries

World map showing GLOBAL FOUNDRIES INCs patent filings in countries

Patent filings per year

Chart showing GLOBAL FOUNDRIES INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Beyer Sven 3
#2 Richter Ralf 2
#3 Baars Peter 2
#4 Yan Ran 2
#5 Hoentschel Jan 2
#6 Cho Jin 2
#7 Yuan Lei 2
#8 Triyoso Dina H 2
#9 Kye Jongwook 2
#10 Trentzsch Martin 2

Latest patents

Publication Filing date Title
US10079597B1 Circuit tuning scheme for fdsoi
US2016357898A1 Temperature-compliant integrated circuits
US9490317B1 Gate contact structure having gate contact layer
US2016266332A1 Optical die packaging
US2016254345A1 Metal-insulator-metal capacitor architecture
US2014167110A1 Partial poly amorphization for channeling prevention
US2015228656A1 REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL
US2015194344A1 Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
US2015187909A1 Methods for fabricating multiple-gate integrated circuits
US2015179740A1 Transistor device with strained layer
US2015162439A1 Semiconductor device including a transistor having a low doped drift region and method for the formation thereof
US9023730B1 Methods for fabricating integrated circuits including generating e-beam patterns for directed self-assembly
US2015076654A1 Enlarged fin tip profile for fins of a field effect transistor (finfet) device
US2015035018A1 Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
US2015024584A1 Methods for forming integrated circuits with reduced replacement metal gate height variability
US2015001628A1 Semiconductor structure with improved isolation and method of fabrication to enable fine pitch transistor arrays
US2014353733A1 Protection of the gate stack encapsulation
US8877625B1 Methods of forming semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting devices
US2014330786A1 Computer-implemented methods and systems for revision control of integrated circuit layout recipe files
US2014264921A1 Through-silicon via with sidewall air gap