US2013069244A1
|
|
Rectangular via for ensuring via yield in the absence of via redundancy
|
US2012223439A1
|
|
Two-track cross-connect in double-patterned structure using rectangular via
|
US2012227015A1
|
|
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process
|
US2012225552A1
|
|
Two-track cross-connects in double-patterned metal layers using a forbidden zone
|
US2012225551A1
|
|
Pattern-split decomposition strategy for double-patterned lithography process
|
US2012331425A1
|
|
Manufacturability enhancements for gate patterning process using polysilicon sub layer
|
US2012148942A1
|
|
Diagonal interconnect for improved process margin with off-axis illumination
|
US2012131522A1
|
|
Method for generating ultra-short-run-length dummy poly features
|
US8138074B1
|
|
ICs with end gates having adjacent electrically connected field poly
|
US2012107729A1
|
|
Gate CD control using local design on both sides of neighboring dummy gate level features
|
US2010167513A1
|
|
Dual alignment strategy for optimizing contact layer alignment
|