Learn more

ARSOVSKI IGOR

Overview
  • Total Patents
    19
About

ARSOVSKI IGOR has a total of 19 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, basic communication technologies and measurement are SENINGEN MICHAEL R, ANOBIT TECHNOLOGIES LTD and CHESEN ELECTRONICS CORP.

Patent filings in countries

World map showing ARSOVSKI IGORs patent filings in countries
# Country Total Patents
#1 United States 19

Patent filings per year

Chart showing ARSOVSKI IGORs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Arsovski Igor 19
#2 Pilo Harold 7
#3 Houle Robert M 4
#4 Wistort Reid A 4
#5 Hill Darryl R 2
#6 Deming Matthew W 2
#7 Braceras George M 2
#8 Thiagarajan Pradeep 2
#9 Cranford Jr Hayden C 2
#10 Ziegerhofer Michael A 2

Latest patents

Publication Filing date Title
US2013326111A1 Content addressable memory early-predict late-correct single ended sensing
US8525546B1 Majority dominant power scheme for repeated structures and structures thereof
US2013223161A1 Vdiff max limiter in SRAMs for improved yield and power
US2012075918A1 SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same
US2012075919A1 Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability
US2012049947A1 Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models
US2011090750A1 SRAM delay circuit that tracks bitcell characteristics
US2011085390A1 Word-line level shift circuit
US2011088005A1 Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM
US2010228861A1 Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes
US2010031067A1 Adaptive noise suppression using a noise look-up table
US2009327620A1 Circuit structure and method for digital integrated circuit performance screening
US2009141566A1 Structure for implementing memory array device with built in computation capability
US2009099828A1 Device Threshold Calibration Through State Dependent Burnin
US2008253042A1 E-fuse and method
US2008046789A1 Apparatus and method for testing memory devices and circuits in integrated circuits