Structure and method for hiding DRAM cycle time behind a burst access
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Method for reducing the width of a global data bus in a memory architecture
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Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies
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Multi-array memory device, and associated method, having shared decoder circuitry
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Enhanced bus turnaround integrated circuit dynamic random access memory device
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Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
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Multi-bank ESDRAM with cross-coupled SRAM cache registers
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Dynamic random access memory word line boost technique employing a boost-on-writes policy
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Multi-array memory device, and associated method, having shared decoder circuitry
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Embedded enhanced DRAM, and associated method
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Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements
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Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
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EDRAM with integrated generation and control of write enable and column latch signals and method for making same
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Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM
