|
US8000135B1
|
|
Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
|
|
US7995388B1
|
|
Data storage using modified voltages
|
|
US7924613B1
|
|
Data storage in analog memory cells with protection against programming interruption
|
|
US2009213654A1
|
|
Programming analog memory cells for reduced variance after retention
|
|
US2009213653A1
|
|
Programming of analog memory cells using a single programming pulse per state transition
|
|
KR20100087277A
|
|
Optimized selection of memory units in multi-unit memory devices
|
|
US8000141B1
|
|
Compensation for voltage drifts in analog memory cells
|
|
US2009091979A1
|
|
Reliable data storage in analog memory cells in the presence of temperature variations
|
|
US7925936B1
|
|
Memory device with non-uniform programming levels
|
|
WO2008139441A2
|
|
Memory device with internal signal processing unit
|
|
CN101715595A
|
|
Adaptive estimation of memory cell read thresholds
|
|
US2008263262A1
|
|
Command interface for memory devices
|
|
US2008181001A1
|
|
Memory device with negative thresholds
|
|
US2008148115A1
|
|
High-speed programming of memory devices
|
|
US2008158958A1
|
|
Memory device with reduced reading latency
|
|
US2008130341A1
|
|
Adaptive programming of analog memory cells using statistical characteristics
|
|
US2008126686A1
|
|
Memory power and performance management
|
|
WO2008053473A2
|
|
Memory cell readout using successive approximation
|
|
US2010165730A1
|
|
Reading memory cells using multiple thresholds
|
|
US2009103358A1
|
|
Reducing programming error in memory devices
|
