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UNITED TEST & ASSEMBLY CT LTD

Overview
  • Total Patents
    51
About

UNITED TEST & ASSEMBLY CT LTD has a total of 51 patent applications. Its first patent ever was published in 2001. It filed its patents most often in United States, Singapore and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets semiconductors, micro-structure and nano-technology and machines are UNISEM MAURITIUS HOLDINGS LTD, MA SHENGPING and SILICON SEMICONDUCTOR CORP.

Patent filings in countries

World map showing UNITED TEST & ASSEMBLY CT LTDs patent filings in countries

Patent filings per year

Chart showing UNITED TEST & ASSEMBLY CT LTDs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Tan Hien Boon 15
#2 Boon Tan Hien 9
#3 Sun Anthony Yi Sheng 8
#4 Tanary Susanto 8
#5 Sun Yi Sheng Anthony 8
#6 Manalac Rodel 7
#7 Wang Chuen Khiang 7
#8 Khiang Wang Chuen 7
#9 Kolan Ravi Kanth 6
#10 Siat Jimmy 6

Latest patents

Publication Filing date Title
JP2010141295A Shrink package on board
DE102009029844A1 Copper wire bonding on organic solder resist materials (OSP) and improved wire bonding process
US2010109169A1 Semiconductor package and method of making the same
SG153762A1 Package-on-package semiconductor structure
US2008293186A1 Method of assembling a silicon stack semiconductor package
SG144124A1 Copper wire bonding on organic solderability preservative materials
SG144112A1 Inverted lead frame on substrate
US2008150106A1 Inverted lead frame in substrate
US2008054435A1 Stacked die packages
SG140574A1 Method of producing a semiconductor package
SG140572A1 Stacked die packages
US2007069371A1 Cavity chip package
US2006202313A1 High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package
US2007246810A1 Leadframe enhancement and method of producing a multi-row semiconductor package
SG122016A1 Semiconductor chip package and method of manufacture
US2008150103A1 Multi-die IC package and manufacturing method
US2005275077A1 High density chip scale leadframe package and method of manufacturing the package
WO2006035321A2 Structurally-enhanced integrated circuit package and method of manufacture
TW200536089A Multiple stacked die window csp package and method of manufacture
WO2004088727A2 Multi-chip ball grid array package and method of manufacture