Learn more

TELA INNOVATIONS INC

Overview
  • Total Patents
    237
  • GoodIP Patent Rank
    16,820
  • Filing trend
    ⇩ 44.0%
About

TELA INNOVATIONS INC has a total of 237 patent applications. It decreased the IP activity by 44.0%. Its first patent ever was published in 2005. It filed its patents most often in United States, Taiwan and Japan. Its main competitors in its focus markets computer technology, semiconductors and environmental technology are LERNER RALF, SILICON SPACE TECHNOLOGY CORP and KUMAR SHAILESH.

Patent filings per year

Chart showing TELA INNOVATIONS INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Becker Scott T 189
#2 Smayling Michael C 119
#3 Quandt Jonathan R 34
#4 Lambert Carole 33
#5 Gandhi Dhrumil 31
#6 Mali Jim 31
#7 Fox Daryl 28
#8 Scott T Becker 21
#9 Gupta Puneet 12
#10 Kahng Andrew B 10

Latest patents

Publication Filing date Title
US2015363542A1 Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
US2014291731A1 Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US2014167117A1 Methods for cell boundary encroachment and layouts implementing the same
US2013256898A1 Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US2013254732A1 Enforcement of semiconductor structure regularity for localized transistors and interconnect
AU2013207719A1 Circuits with linear finfet structures
US2011156167A1 Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same
US2010006951A1 Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US2010006901A1 Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
EP3327594A1 Methods for cell phasing and placement in dynamic array architecture and implementation of the same
KR20160031041A Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US2009224408A1 Methods for multi-wire routing and apparatus implementing same
US2009224317A1 Cross-coupled transistor layouts in restricted gate level layout architecture
US2009127636A1 Diffusion variability control and transistor device sizing using threshold voltage implant
US7865856B1 System and method for performing transistor-level static performance analysis using cell-level static analysis tools
TW201820190A Semiconductor chip
US2010306719A1 Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US2009037864A1 Methods for designing semiconductor device with dynamic array section
US2009108360A1 Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7577049B1 Speculative sense enable tuning apparatus and associated methods