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Method and system for generating CRT timing signals in a graphics accelerator
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Method and system for concurrent processing of slices of a bitstream in a multiprocessor (MP) system
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Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal
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Method and structure for refresh operation with a low voltage of logic high in a memory device
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Circuit and method for reducing delay line length in delay-locked loops
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Method and system for improved memory interface during image rendering
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Self-bootstrapping word-line driver circuit and method
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Redundancy programming circuit and system for semiconductor memory
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Dual-edge extended data out memory
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Circuit and method for reducing lock-in time in phase-locked and delay-locked loops
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Method and system for improved z-test during image rendering
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System and method for providing efficient access to a memory bank
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Adaptive auto refresh
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DRAM implementation for more efficient use of silicon area
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