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High-speed semiconductor memory having internal refresh control
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Multi-bit parallel testing for memory devices
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Method and circuit for processing output data in pipelined circuits
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Delay-locked loop for differential clock signals
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Memory device with time shared data lines
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High speed memory architecture and busing
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Data input/output system for multiple data rate memory devices
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Controlling the set up of a memory address
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Hierarchical decoding of a memory device
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Memory device having a wide data path
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Multiple equilibration circuits for a single bit line
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