|
US10505550B1
|
|
Method and apparatus of operating synchronizing high-speed clock dividers to correct clock skew
|
|
US2019363729A1
|
|
High-speed DAC
|
|
US2019268193A1
|
|
PWM demodulation
|
|
US2019253284A1
|
|
Receiver for handling high speed transmissions
|
|
US10061340B1
|
|
Bandgap reference voltage generator
|
|
US2019072589A1
|
|
Digital voltmeter
|
|
US10094859B1
|
|
Voltage detector
|
|
US2019028090A1
|
|
Duty cycle detection
|
|
US2018164163A1
|
|
Temperature sensing for integrated circuits
|
|
US9716492B1
|
|
Method and circuit for duty cycle detection
|
|
US2017373696A1
|
|
Clock alignment scheme for data macros of DDR PHY
|
|
US9564180B1
|
|
Deep-sleep wake up for a memory device
|
|
US9613700B1
|
|
TCAM field enable logic
|
|
US9715907B1
|
|
Optimal data eye for improved Vref margin
|
|
US2017316837A1
|
|
Diagnostics for a memory device
|
|
US2016224450A1
|
|
Memory built-in self test system
|
|
US2016224451A1
|
|
Multi-domain fuse management
|
|
US2016148655A1
|
|
Sense amplifier and methods thereof for single ended line sensing
|
|
US2016218717A1
|
|
Voltage level shifter
|
