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SANDHU GURTEJ S

Overview
  • Total Patents
    69
About

SANDHU GURTEJ S has a total of 69 patent applications. Its first patent ever was published in 2003. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, micro-structure and nano-technology and computer technology are HYUNDAI ELECTRONICS INDUSTRY C, BHATTACHARYYA ARUP and XU HUIWEN.

Patent filings in countries

World map showing SANDHU GURTEJ Ss patent filings in countries
# Country Total Patents
#1 United States 69

Patent filings per year

Chart showing SANDHU GURTEJ Ss patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Sandhu Gurtej S 69
#2 Srinivasan Bhaskar 5
#3 Mouli Chandra 3
#4 Prall Kirk D 3
#5 Durcan D Mark 2
#6 Parat Krishna K 2
#7 Blalock Guy T 2
#8 Smythe Iii John A 2
#9 Rericha William T 2
#10 Ramaswamy D V Nirmal 2

Latest patents

Publication Filing date Title
US2014070342A1 Methods of forming magnetic memory cells
US2013294145A1 Switching device structures and methods
US8558209B1 Memory cells having-multi-portion data storage region
US2013250661A1 Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication
US2013248797A1 Memory cells
US2013214242A1 Integrated circuitry components, switches, and memory cells
US2013193400A1 Memory Cell Structures and Memory Arrays
US2013187117A1 Memory cells
US2013069052A1 Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
US2013049120A1 Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US2013028016A1 Memory cells and methods of storing information
US2013029460A1 Methods of forming graphene-containing switches
US2013001495A1 Multilevel mixed valence oxide (MVO) memory
US2012302028A1 Mixed valent oxide memory and method
US2012230128A1 Integrated circuitry, switches, and methods of selecting memory cells of a memory device
US2012223277A1 Sliver structure and method of handling sliver structures
US2012051132A1 Memory cell structures and methods
US2012006580A1 Electrically conductive laminate structure containing graphene region
US2011261606A1 Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US2011248778A1 Semiconductor devices including gate structures comprising colossal magnetocapacitive materials