|
US2007063186A1
|
|
Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
|
|
US2007063185A1
|
|
Semiconductor device including a front side strained superlattice layer and a back side stress layer
|
|
WO2007011790A1
|
|
Semiconductor device including a channel with a non-semiconductor monolayer and associated methods
|
|
WO2007011627A1
|
|
Semiconductor device including a strained superlattice layer above a stress layer and associated methods
|
|
EP1905091A1
|
|
Semiconductor device including a strained superlattice and overlying stress layer and related methods
|
|
US2007012910A1
|
|
Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
|
|
US2007010040A1
|
|
Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
|
|
US2007020860A1
|
|
Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
|
|
US2007020833A1
|
|
Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
|
|
US2007015344A1
|
|
Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
|
|
US2006289049A1
|
|
Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
|
|
US2006292765A1
|
|
Method for Making a FINFET Including a Superlattice
|
|
US2006292889A1
|
|
FINFET including a superlattice
|
|
US2006267130A1
|
|
Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
|
|
WO2006130665A2
|
|
Microelectromechanical systems (mems) device including a superlattice and associated methods
|
|
US2006223215A1
|
|
Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
|
|
US2006231857A1
|
|
Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
|
|
US2006243964A1
|
|
Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
|
|
US2006220118A1
|
|
Semiconductor device including a dopant blocking superlattice
|
|
US2006273299A1
|
|
Method for making a semiconductor device including a dopant blocking superlattice
|
