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CHANG JOSEPHINE B

Overview
  • Total Patents
    64
About

CHANG JOSEPHINE B has a total of 64 patent applications. Its first patent ever was published in 2009. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets semiconductors, micro-structure and nano-technology and machines are RADOSAVLJEVIC MARKO, NITEK INC and CAPPELLANI ANNALISA.

Patent filings in countries

World map showing CHANG JOSEPHINE Bs patent filings in countries

Patent filings per year

Chart showing CHANG JOSEPHINE Bs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Chang Josephine B 64
#2 Sleight Jeffrey W 36
#3 Guillorn Michael A 28
#4 Lin Chung-Hsun 28
#5 Lauer Isaac 16
#6 Chang Leland 13
#7 Chang Paul 8
#8 Majumdar Amlan 4
#9 Han Shu-Jen 4
#10 Engelmann Sebastian U 4

Latest patents

Publication Filing date Title
US2014073106A1 Lateral bipolar transistor and cmos hybrid technology
US8617957B1 Fin bipolar transistors having self-aligned collector and emitter regions
US8586449B1 Raised isolation structure self-aligned to fin structures
US2014065802A1 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
US2014051225A1 Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
US2014051213A1 Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices
US8536029B1 Nanowire FET and finFET
US2013328116A1 DRAM with a nanowire access transistor
US2013320422A1 Finfet contacting a conductive strap structure of a dram
US2013320399A1 Embedded planar source/drain stressors for a finFET including a plurality of fins
US2013285142A1 Narrow body field-effect transistor structures with free-standing extension regions
US2013277758A1 Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric
US2013260516A1 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
US2013214357A1 Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same
US8466012B1 Bulk FinFET and SOI FinFET hybrid technology
US2013175623A1 Recessed source and drain regions for FinFETs
US2013153993A1 Hybrid CMOS nanowire mesh device and FINFET device
US2013153997A1 Hybrid CMOS nanowire mesh device and bulk CMOS device
US2013153996A1 Hybrid CMOS nanowire mesh device and PDSOI device
US2013109167A1 Nanowire efuses