|
US2016062656A1
|
|
Command Set Extension for Non-Volatile Memory
|
|
US2015293810A1
|
|
Content addressable memory with error detection
|
|
US2015006827A1
|
|
Method for detecting bank collision at a memory and device therefor
|
|
US2014269131A1
|
|
Memory with power savings for unnecessary reads
|
|
US2013290753A1
|
|
Memory column drowsy control
|
|
US8493121B1
|
|
Reconfigurable flip-flop
|
|
US2014052931A1
|
|
Data type dependent memory scrubbing
|
|
US2014052924A1
|
|
Selective memory scrubbing based on data type
|
|
US2014003172A1
|
|
Memory with word line access control
|
|
US8487656B1
|
|
Dynamic logic circuit
|
|
US2013283126A1
|
|
Error detection within a memory
|
|
US2013268732A1
|
|
System and method for cache access
|
|
US2013238875A1
|
|
Multiple page size memory management unit
|
|
US2013227368A1
|
|
Hierarchical error correction
|
|
US2013046927A1
|
|
Memory management unit TAG memory with CAM evaluate signal
|
|
US2012306556A1
|
|
Double edge triggered flip flop
|
|
US2012274307A1
|
|
Voltage regulator with different inverting gain stages
|
|
US2012233498A1
|
|
Hierarchical error correction for large memories
|
|
US2012230126A1
|
|
Memory voltage regulator with leakage current voltage control
|
|
US2012200336A1
|
|
Electronic circuit having shared leakage current reduction circuits
|
