US6584611B2
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Critical path optimization—unload hard extended scalar block
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US6718541B2
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Register economy heuristic for a cycle driven multiple issue instruction scheduler
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US6751645B1
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Methods and apparatus for performing pipelined SRT division
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US6567831B1
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Computer system and method for parallel computations using table approximation
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US6323688B1
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Efficient half-cycle clocking scheme for self-reset circuit
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US6526573B1
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Critical path optimization-optimizing branch operation insertion
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US6366130B1
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High speed low power data transfer scheme
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US6594824B1
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Profile driven code motion and scheduling
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US6424181B1
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High-speed low-power sense amplifying half-latch and apparatus thereof for small-swing differential logic (SSDL)
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US6373149B1
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Power supply control for low voltage circuits using high threshold switch transistors
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US6351155B1
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High-speed sense amplifier capable of cascade connection
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US6313691B1
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Method and apparatus for adjusting the static thresholds of CMOS circuits
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US6549903B1
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Integrity of tagged data
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US6265896B1
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Level transfer circuit for LVCMOS applications
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US6320446B1
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System for improving low voltage CMOS performance
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US6564372B1
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Critical path optimization-unzipping
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US6668316B1
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Method and apparatus for conflict-free execution of integer and floating-point operations with a common register file
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US6363405B1
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Computer system and method for parallel computations using table approximation methods
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US6412105B1
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Computer method and apparatus for compilation of multi-way decisions
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US6560775B1
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Branch preparation
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