WO2010053603A1
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Method for piecewise hierarchical sequential verification
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Physical realization of dynamic logic using parameterized tile partitioning
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Expansion syntax
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Null value propagation for FAST14 logic
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Static storage element for dynamic logic
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Static transmission of FAST14 logic 1-of-N signals
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Monitor manager that creates and executes state machine-based monitor instances in a digital simulation
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Rearranging data between vector and matrix forms in a SIMD matrix processor
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Generation of route rules
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Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index
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Random number indexing method and apparatus that eliminates software call sequence dependency
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Dynamic logic scan gate method and apparatus
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Method for calculating dynamic logic block propagation delay targets using time borrowing
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Rounding anticipator for floating point operations
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Method and apparatus for pre-branch instruction
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Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state
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Dynamic logic scan gate method and apparatus
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Method and apparatus for scan of synchronized dynamic logic using embedded scan gates
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AU2712300A
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Method and apparatus for routing 1 of n signals
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Method and apparatus that reports multiple status events with a single monitor
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