CN107710325A
|
|
A kind of FPGA circuitry and its configuration file processing method
|
WO2017113358A1
|
|
Universal interface of programmable logic block array edge and chip
|
CN110313002A
|
|
A kind of fpga chip wiring method based on PLB
|
WO2017084104A1
|
|
Fpga-based look-up table technology mapping method and look-up table
|
CN106709119A
|
|
FPGA chip wiring method
|
CN107005240A
|
|
A kind of adder wiring method for supporting pin to exchange
|
CN106649905A
|
|
Technology mapping method by utilizing carry chain
|
CN105404728A
|
|
FPGA based chip multi-control signal layout method
|
CN106649898A
|
|
Method for packing and deploying adders
|
CN106649899A
|
|
Local memory layout method
|
WO2017020169A1
|
|
Hot swap protection circuit
|
WO2017012072A1
|
|
Circuit and method for power-on initialization of fpga configuration memory
|
WO2016201607A1
|
|
Chip power supply method and chip
|
CN106292816A
|
|
A kind of LDO circuit and method of supplying power to, fpga chip
|
CN106301355A
|
|
A kind of device of multiphase clock output
|
CN106301361A
|
|
Decimal frequency divider and decimal frequency dividing method
|
CN106301354A
|
|
A kind of duty cycle correction device and method
|
CN106664012A
|
|
Charge pump and electronic device comprising same
|
US2017111047A1
|
|
Buffer circuit and electronic device using same
|
CN106133838A
|
|
A kind of expansible configurable FPGA storage organization and FPGA device
|