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PENDSE RAJENDRA D

Overview
  • Total Patents
    48
About

PENDSE RAJENDRA D has a total of 48 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, audio-visual technology and environmental technology are TOPACIO RODEN R, CHOW SENG GUAN and CHANDRASEKARAN ARVIND.

Patent filings in countries

World map showing PENDSE RAJENDRA Ds patent filings in countries
# Country Total Patents
#1 United States 48

Patent filings per year

Chart showing PENDSE RAJENDRA Ds patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Pendse Rajendra D 48
#2 Kim Kyungoe 5
#3 Kang Taewoo 5
#4 Chow Seng Guan 2
#5 Carson Flynn 2
#6 Shim Il Kwon 2
#7 Lee Taekeun 1
#8 Han Byung Joon 1
#9 Kim Youngcheol 1
#10 Joshi Mukul 1

Latest patents

Publication Filing date Title
USRE44438E Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US2012223428A1 Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US2013161833A1 Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
US2011309500A1 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US2011306168A1 Integrated circuit package system for package stacking and method of manufacture thereof
US2011084386A1 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US2011304058A1 Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US2011074028A1 Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US2011133334A1 Semiconductor device and method of confining conductive bump material with solder mask patch
US2011248399A1 Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US2011076809A1 Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US2011074047A1 Semiconductor device and method of forming pad layout for flipchip semiconductor die
US2011074024A1 Semiconductor device and method of forming bump-on-lead interconnection
US2011074022A1 Semiconductor device and method of forming flipchip interconnect structure
US2011233763A1 Integrated circuit system with stress redistribution layer and method of manufacture thereof
US2010099222A1 Solder joint flip chip interconnection having relief structure
US2010164097A1 Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US2010065966A1 Solder joint flip chip interconnection
US2010007019A1 Semiconductor device and method of forming composite bump-on-lead interconnection
US2009289253A1 Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test