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PDF SOLUTIONS INC

Overview
  • Total Patents
    247
  • GoodIP Patent Rank
    10,808
  • Filing trend
    ⇩ 56.0%
About

PDF SOLUTIONS INC has a total of 247 patent applications. It decreased the IP activity by 56.0%. Its first patent ever was published in 1999. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and China. Its main competitors in its focus markets semiconductors, computer technology and measurement are ADVANCED MIRCO DEVICES INC, LERNER RALF and ASPEC TECH INC.

Patent filings per year

Chart showing PDF SOLUTIONS INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Hess Christopher 137
#2 Haigh Jonathan 96
#3 Kibarian John 95
#4 Ciplickas Dennis 94
#5 Michaels Kimon 92
#6 Lee Sherry 91
#7 De Indranil 89
#8 Weiland Larg 88
#9 Lam Stephen 86
#10 Brozek Tomasz 86

Latest patents

Publication Filing date Title
CN112230067A Resistance testing structure and method
WO2021076937A1 Die level product modeling without die level input data
WO2021076943A1 Machine learning variable selection and root cause discovery by cumulative prediction
WO2021076609A1 Collaborative learning model for semiconductor applications
US2021103489A1 Anomalous Equipment Trace Detection and Classification
US2021098229A1 Systems, devices, and methods for aligning a particle beam and performing a non-contact electrical measurement on a cell and/or non-contact electrical measurement cell vehicle using a registration cell
US2021096179A1 Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block
CN111401420A Abnormal data clustering method and device for wafer test, electronic equipment and medium
CN111341685A Abnormal value detection method and device for bare chip, electronic equipment and storage medium
CN111368928A Wafer pattern matching method and device, electronic equipment and storage medium
CN111352752A System, method and device for processing semiconductor test data and server
US10978438B1 IC with test structures and E-beam pads embedded within a contiguous standard cell area
US2019304849A1 Selective inclusion/exclusion of semiconductor chips in accelerated failure tests
US10679723B1 Direct memory characterization using periphery transistors
US10565344B1 Standard cell design conformance using boolean assertions
US2019320525A1 Characterization vehicles for printed circuit board and system design
US2019146032A1 Failure detection for wire bonding in semiconductors
US10643735B1 Passive array test structure for cross-point memory characterization
US10768222B1 Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure
US10199283B1 Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage