Process for manufacturing a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate which stores charge on inner and outer surfaces
US5541137A
Method of forming improved contacts from polysilicon to silicon or other polysilicon layers
US5439835A
Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5494841A
Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells
US5484314A
Micro-pillar fabrication utilizing a stereolithographic printing process
US5466639A
Double mask process for forming trenches and contacts during the formation of a semiconductor memory device
US5405791A
Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers
US5528539A
High speed global row redundancy system
US5414376A
Programmable logic device macrocell having exclusive lines for feedback and external input, and a node which is selectively shared for registered output and external input
US5455801A
Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal
US5465232A
Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory
US5438019A
Large area thin film growing method
US5376577A
Method of forming a low resistive current path between a buried contact and a diffusion region
US5393694A
Advanced process for recessed poly buffered locos
US5418180A
Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon
US5496762A
Highly resistive structures for integrated circuits and method of manufacturing the same
DE4419074A1
Method for uniformly doping polycrystalline silicon with hemispherical grain
US5444279A
Floating gate memory device having discontinuous gate oxide thickness over the channel region
