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Growing a III-V layer on silicon using aligned nano-scale patterns
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Formation of III-V based devices on semiconductor substrates
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Fin structure for high mobility multiple-gate transistor
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Source/drain re-growth for manufacturing III-V based transistors
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Source/drain engineering of devices with high-mobility channels
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Gradient ternary or quaternary multiple-gate transistor
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Reducing source/drain resistance of III-V based transistors
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MOS devices having elevated source/drain regions
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CMOS devices with schottky source and drain regions
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Capacitor-less 1T-DRAM cell with Schottky source and drain
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Isolation structure for strained channel transistors
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