|
WO2010114890A1
|
|
Techniques for providing a semiconductor memory device
|
|
WO2010102106A2
|
|
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
|
|
WO2009100054A1
|
|
Integrated circuit having memory cells including gate material having high work function, and method of manufacturing the same
|
|
WO2009068548A1
|
|
Integrated circuit having memory cell array including barriers, and method of manufacturing same
|
|
US2009067218A1
|
|
Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same
|
|
KR20100024396A
|
|
Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
|
|
KR20100014848A
|
|
Floating-body dram transistor comprising source/drain regions separated from the gated body region
|
|
US2008013359A1
|
|
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
|
|
US2007268761A1
|
|
Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same
|
|
US2007241405A1
|
|
Semiconductor memory array architecture with grouped memory cells, and method of controlling same
|
|
US2007285982A1
|
|
Memory array having a programmable word length, and method of operating same
|
|
US2007187775A1
|
|
Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
|
|
US2008165605A1
|
|
Method and apparatus for variable memory cell refresh
|
|
US2007138530A1
|
|
Electrically floating body memory cell and array, and method of operating or controlling same
|
|
US2007058427A1
|
|
Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
|
|
US2006091462A1
|
|
Memory cell having an electrically floating body transistor and programming technique therefor
|
