|
WO2009039169A1
|
|
Refreshing data of memory cells with electrically floating body transistors
|
|
WO2009031052A2
|
|
Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor
|
|
WO2008002513A2
|
|
Integrated circuit having memory array including ecc and/or column redundancy, and method of programming, controlling and/or operating same
|
|
US2007064489A1
|
|
Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
|
|
US2006131650A1
|
|
Bipolar reading technique for a memory cell having an electrically floating body transistor
|
|
US2006126374A1
|
|
Sense amplifier circuitry and architecture to write data into and/or read from memory cells
|
|
US2006098481A1
|
|
Circuitry for and method of improving statistical distribution of integrated circuits
|
|
US7187581B2
|
|
Semiconductor memory device and method of operating same
|
|
US7184298B2
|
|
Low power programming technique for a floating body memory transistor, memory cell, and memory array
|
|
US7335934B2
|
|
Integrated circuit device, and method of fabricating same
|
|
US7085153B2
|
|
Semiconductor memory cell, array, architecture and device, and method of operating same
|
|
EP1357603A2
|
|
Semiconductor device
|
|
EP1355316A1
|
|
Data storage device and refreshing method for use with such device
|
|
TWI230392B
|
|
Semiconductor device
|
|
EP1355361A1
|
|
Method of forming an electric charge in a body of a semiconductor component
|
|
EP1355357A1
|
|
Electrical charge carrier semiconductor device
|
|
EP1351307A1
|
|
Method of driving a semiconductor device
|
|
EP1271547A1
|
|
Semiconductor device and DRAM
|
