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Memory cell and memory array select transistor
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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
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A memory device comprising an electrically floating body transistor
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Memory cells, memory cell arrays, methods of using and methods of making
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Method of maintaining the state of semiconductor memory having electrically floating body transistor
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Memory device comprising an electrically floating body transistor and methods of using
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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
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A mosfet and memory cell having improved drain current through back bias application
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Forming semiconductor cells with regions of varying conductivity
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Content addressable memory device having electrically floating body transistor
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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
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Memory device comprising electrically floating body transistor
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Memory device comprising electrically floating body transistor
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Memory device comprising an electrically floating body transistor
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Systems and methods for reducing standby power in floating body memory devices
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NAND string utilizing floating body memory cell
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Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers
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Memory cell comprising first and second transistors and methods of operating
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Semiconductor memory device having electrically floating body transistor, and having both volatile and non-volatile functionality and method
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